1. Field of the Invention
The present invention relates to a capacitor of a semiconductor device, and a method for forming the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, there is a necessity for reducing the area occupied by a capacitor, which in turn causes a reduction in the capacitance. To solve this problem, the structure of the capacitor is changed or a material having a high dielectric constant is employed. For instance, a method has been proposed for forming a capacitor using a Ta2O5 dielectric layer or a (Ba,Sr)TiO3 (BST) dielectric layer having a dielectric constant higher than that of an oxide/nitride/oxide (ONO) layer structure typically used for a dynamic random access memory (DRAM).
However, the process is complicated. The structure of a typical capacitor is a silicon/insulator/silicon (SIS) layer structure in which polycrystalline silicon layers doped with an impurity are used for plate and storage nodes. However, a metal/insulator/silicon (MIS) layer or a metal/insulator/metal (MIM) layer structure is required for the case of using the Ta2O5 layer, and the MIM layer structure is required for the case of using the BST layer. That is, the structure of the capacitor must be changed.
If the Ta2O5 layer is used, then in order to overcome low step coverage, a layer must be formed using chemical vapor deposition (CVD) at a low temperature, which is a surface kinetic regime, and which may cause a deficiency in oxygen, leaving hydrocarbon residue in the layer or deterioration in crystallization. Thus, the dielectric constant is reduced, and insulating properties are poor. Accordingly, to overcome these problems, a dry O2 annealing process at a high temperature is additionally required. Also, there has been disclosed a method for compensating for the insulating properties of the Ta2O5 layer by using an oxide layer under the Ta2O5 layer generated by a dry annealing process (Y. Ohyi, xe2x80x9cTa2O5 Capacitor Dielectric Material for Giga-bit DRAMsxe2x80x9d, IEDM Tech. Dig., 1994. p831).
Meanwhile, diffusion is easily caused by discontinuities in the atomic arrangement at a grain boundary. Thus, when a thick oxide layer is formed to compensate for the leakage current properties of the Ta2O5 layer, diffusion of oxygen into the grain boundary is increased, to thereby oxidize a plate node. Accordingly, a reaction preventing layer is required between the Ta2O5 layer and the plate node of the capacitor to prevent reaction of the Ta2O5 layer with the plate node (U.S. Pat. No. 4,891,684).
In order to obtain excellent leakage current properties, a schottky barrier must be formed between a BST layer and an electrode. In order to form the Schottky barrier, an electrode should be formed of materials having a high work function, e.g., a metal (see Soon Oh Park, xe2x80x9cFabrication and Electrical Characterization of Pt/(Ba, Sr)TiO3/Pt Capacitors for Ultralarge-scale Integrated Dynamic Random Access Memory Applicationsxe2x80x9d, Jpn. J. Appl. Phys. Vol. 35,1996, pp. 1548-1552). In order to employ the metal electrode, an ohmic contact must be formed at an interface between the metal electrode and the polycrystalline silicon layer doped with an impurity. That is, an intermediate layer forming the ohmic contact must be formed and a barrier layer must be employed.
The material layer of a high dielectric constant, such as the Ta2O5 layer or the BST layer, requires a complicated process and structure, that is, a change of the structure of the capacitor to the MIM or MIS structure.
It is an object of the present invention to provide a capacitor of a semiconductor device, using a silicon-containing conductive layer as a storage node to increase capacitance.
It is another object to provide a method for forming a capacitor of a semiconductor device, using a silicon-containing conductive layer as a storage node to increase capacitance. Other and further objects will appear hereafter.
Accordingly, to achieve one objective, the capacitor of the present invention includes a storage node, a dielectric layer and a plate node. The storage node is a silicon-containing conductive layer such as a polycrystalline silicon layer doped with an impurity. Also, the storage node has a three dimensional structure selected from the group consisting of a stack type, a hemispherical grained silicon layer type and a cylinder type.
The dielectric layer is formed of amorphous Al2O3, on the storage node. Here, the amorphous Al2O3 layer is formed by transmitting vapor reactive materials supplied by each source to the storage node in which reactions are sequentially processed. The thickness of the dielectric layer is 10xcx9c300 xc3x85 using an atomic layered deposition method, and the thickness of the amorphous Al2O3 dielectric layer is 40xcx9c70 xc3x85. Also, a reaction preventing layer is formed of one selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride layer.
The plate node is a conductive layer formed of polycrystalline silicon doped with impurities. Alternatively, the plate node is a conductive layer formed of a refractory metal, a refractory metal silicide material or a refractory metal nitride material. For example, the refractory metal may be W, Mo, Ta, Ti or Cr. Also, the refractory metal silicide material is formed by silicidation of a refractory metal silicide material, such as Wsi2, MoSi2, TaSi2 or TiSi2, among others. The refractory metal nitride material is formed by nitrification of a refractory metal, such as TiN.
To achieve another objective, a storage node is formed. The storage node is a polycrystalline silicon layer doped with an impurity, and the storage node has a three-dimensional structure selected from the group consisting of a stack type, a hemispherical grained silicon layer type and a cylinder type.
Then, a reaction preventing layer is formed on the storage node. The reaction preventing layer is formed by annealing the storage node at 300xcx9c1200xc2x0 C. In detail, a rapid thermal nitridation (RTN) process is performed using a N2 source such as NH3 gas as an ambient gas at approximately 900xc2x0 C. Thus, the reaction preventing layer of the storage node may be formed of silicon oxide (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON).
Next, a dielectric layer is formed of an amorphous Al2O3 layer on the storage node. The amorphous Al2O3 layer is formed to a thickness of 10-300 xc3x85 by a method of supplying a reactive vapor phase material from each of several sources in sequence on a layer to be reacted with, i.e., the storage node, in which reaction, that is, deposition is performed in cycles, for instance, an atomic layer deposition (ALD) method. Preferably, the amorphous Al2O3 layer is formed to a thickness of 40-80 xc3x85. The atomic layer deposition method is performed using one selected from the group consisting of Al(CH3)3 and AlCl3 as an aluminum source, and the storage node is processed by hydrogen passivation treatment before performing the atomic layered deposition.
Then, a plate electrode is formed on the dielectric layer. The plate node is a conductive layer formed of polycrystalline silicon doped with impurities. Alternatively, the plate node is a conductive layer formed of a refractory metal, a refractory metal silicide material or a refractory metal nitride material. For example, the refractory metal may be W, Mo, Ta, Ti or Cr. Also, the refractory metal silicide material is formed by silicidation of a refractory metal silicide material, such as WSi2, MoSi2, TaSi2 or TiSi2, among others. The refractory metal nitride material is formed by nitrification of a refractory metal, such as TiN.
Also, a primary densification is performed on the amorphous Al2O3 dielectric layer, after the step of forming a plate node, by annealing the amorphous Al2O3 dielectric layer at a temperature below the temperature of crystallizing the amorphous Al2O3 layer, at 150-900xc2x0 C. The annealing is performed using an ambient gas selected from the group consisting of O2, NO and N2 gas, or in a vacuum. Preferably, the primary densification is performed at 850xc2x0 C.
Also, a secondary densification is additionally performed on the amorphous Al2O3 dielectric layer, before the step of forming a plate node, by annealing the amorphous Al2O3 dielectric layer at a temperature below the temperature of crystallizing the amorphous Al2O3 layer, at 150-900xc2x0 C., using an ambient gas selected from the group consisting of O2, NO and N2 gas, or in a vacuum. Preferably, the annealing is performed using O2 as an ambient gas at approximately 450xc2x0 C.
Accordingly, the silicon-containing conductive layer is used as the storage node, and the capacitance can be increased.